1. Field of the Invention
The present invention relates generally to methods for forming patterned layers within integrated circuits. More particularly, the present invention relates to methods for forming within integrated circuits patterned layers of linewidth at least as narrow as about 0.25 microns while employing i-line (ie: 365 nm) photoexposure radiation.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by insulator layers.
As integrated circuit technology has advanced, there has been a continuing and correlating trend towards decreasing linewidth dimensions of electrical circuit elements and patterned layers through which are formed those advanced integrated circuits. The decreasing linewidth dimensions have typically traditionally been effected principally through decreasing the wavelength of photoexposure radiation employed in forming patterned photoresist layers which are employed in defining the linewidth dimensions of those electrical circuit elements and patterned layers. Currently, photoexposure radiation is typically in the near ultra-violet (NUV) (ie: 365 nm) wavelength region for forming electrical circuit elements and patterned layers of linewidth dimension typically as low as about 0.30 micron, while the most advanced photoexposure tooling typically employs a photoexposure radiation in the deep ultra-violet (DUV) (ie: 248 nm) wavelength region or x-ray wavelength region for forming electrical circuit elements and patterned layers of linewidth dimensions in the deep sub-micron region as low as about 0.10 micron.
While the trend towards decreasing wavelength of photoexposure radiation as a means for providing electrical circuit elements and patterned layers of decreased linewidth dimensions within advanced integrated circuits will most certainly continue, it nonetheless becomes important to provide methods and materials through which the evolution from the current generations of integrated circuits having formed therein electrical circuit elements and patterned layers defined by photoexposure tooling employing a near ultra-violet (NUV) (ie: 365 nm) photoexposure radiation wavelength to future generations of integrated circuits having formed therein electrical circuit elements and patterned layers defined by advanced generations of photoexposure tooling employing a deep ultra-violet (DUV) (ie: 248 nm) or x-ray photoexposure radiation wavelength may be smoothly facilitated. In that regard, it is typically desirable to characterize to the extent possible, through relevant research and development activities, advanced electrical circuit elements and patterned layers of decreased linewidth dimensions at the earliest possible opportunity prior to committing production of integrated circuits having formed therein those advanced electrical circuit elements and patterned layers of decreased linewidth dimensions to advanced photoexposure tooling. Among other advantages, such pre-production characterization allows for efficient use of advanced photoexposure tooling when initiating production of the advanced integrated circuits within a manufacturing environment. In particular, within advanced integrated circuits having formed therein advanced field effect transistors (FETs) defined by gate electrodes of diminished linewidth dimensions, it is typically desirable to fully characterize those advanced field effect transistors (FETs) prior to production of those advanced field effect transistors (FETs) since the gate electrode linewidth within a field effect transistor (FET) defines the channel width within the field effect transistor (FET) which in part defines the operational characteristics of the field effect transistor (FET). It is thus towards providing a method for forming within advanced integrated circuits advanced electrical circuit elements and patterned layers having decreased linewidth dimensions without the need for employing advanced photoexposure tooling in forming those advanced electrical circuit elements and patterned layers that the present invention is generally directed.
Plasma etch methods and materials which may be employed in forming within integrated circuits patterned layers, such as patterned polysilicon or polycide gate electrodes within field effect transistors (FETs), are known in the art of integrated circuit fabrication. For example, plasma etchant gases appropriate for etching layers formed of various materials within integrated circuits are in general disclosed by S. Wolf et al. in Silicon Processing for the VLSI Era, Vol. 1: Process Technology, Lattice Press (Sunset Beach, Calif.; 1968), pg. 581. In addition, Jacob, in U.S. Pat. No. Re. 30,505 discloses, for the etching of integrated circuit layers including insulator layers and several metal layers, several specific reactive ion etch (RE) etchant gas compositions employing binary mixtures of oxygen and halocarbons of no greater than two carbon atoms, where at least one of the carbon atoms is linked to a predominance of fluorine atoms. Further, Kook et al., in U.S. Pat. No. 5,326,727 discloses a specific method and materials for limiting etch bias during plasma etching when forming patterned layers within integrated circuits. The method employs an organic planarizing layer and a plasma etchant gas composition comprising oxygen and a halogen or halogen hydride. Analogously, Ta et al., in U.S. Pat. No. 5,308,742 disclose another plasma etch method and materials for limiting etch bias during plasma etching when forming patterned layers within integrated circuits. The method employs an organic anti-reflective coating (ARC) layer and a plasma etchant gas composition comprising trifluoromethane, oxygen and argon. Finally, various types of anti-reflective coating (ARC) layer compositions are in general disclosed Flaim et al., in U.S. Pat. No. 5,368,989, the teachings of which are incorporated herein fully by reference.
Most pertinent to the present invention, however, is the disclosure within a related co-assigned application similarly entitled "Method for Controlling Linewidth by Etching Bottom Anti-Reflective Coating," application Ser. No. 08/711,142, filed Sep. 9, 1996, now U.S. Pat. No. 5,773,199, which describes a plasma etch method employing a focusing layer formed from an organic anti-reflective coating (ARC) material and a plasma etchant gas composition comprising trifluoromethane, carbon tetrafluoride, oxygen and argon. Through the plasma etch method there may be formed within integrated circuits patterned layers of linewidth dimensions at least as narrow as about 0.25 microns while employing near ultra-violet (NUV) (ie: 365 nm) photoexposure radiation. While the method and materials as disclosed within application Ser. No. 08/711,142 provide within integrated circuits patterned layers of linewidth dimension at least as narrow as about 0.25 microns, the method is not entirely without problems. In particular, within the method as disclosed within application Ser. No. 08/1711,142 there is typically observed: (1) a substantial variation in linewidth dimensions of patterned layers formed through the method; and (2) an elevated level of particulate contamination formed upon patterned layers formed through the method. It is towards addressing at least one of these two problems that the present invention is directed.
Thus, desirable in the art are additional methods and materials through which linewidth dimensions of electrical circuit elements and patterned layers within advanced integrated circuits may be controlled. Particularly desirable are methods and materials through which linewidth dimensions of electrical circuit elements and patterned layers within advanced integrated circuits may be controlled to provide electrical circuit elements and patterned layers of linewidth dimension at least as narrow as about 0.25 microns while employing near ultra-violet (NUV) (ie: 365 nm) photoexposure radiation. More particularly desirable are additional methods and materials through which advanced field effect transistors (FETs) having gate electrodes of linewidth dimension at least as narrow as about 0.25 microns may be formed within advanced integrated circuits while employing near ultra-violet (NUV) (ie: 365 nm) photoexposure radiation. Most particularly desirable are methods and materials which fulfill the foregoing criteria while providing patterned layers of uniform linewidth dimensions and/or minimal particulate contamination. It is towards these goals that the present invention is specifically directed.